Optical Contactless Testing

2 0740-7475/06/$20.00 © 2006 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers WITH DECREASING FEATURE SIZE and increasing chip densities, the classical mechanical probe approach for internal fault detection and functional testing faces increasing challenges. Mechanical probes have limitations because of their relatively large size and inherent parasitic effects. The Semiconductor Industry Association’s 2003 International Technology Roadmap for Semiconductors (ITRS) predicts that ASICs will require more than 4,000 I/O pads for the next three years, with a peripheral pitch distance of 30 μm (http://public.itrs.net/Files/2003ITRS/ Home2003.htm). Such large I/O counts challenge testing reliability in numerous ways; for example, assuring reliable ohmic contact to all test pads during repeated die tests is becoming a significant concern. DFT approaches are valuable techniques for helping solve the growing test problem. However, as the ITRS suggests, they alone do not offer a solution. Contactless testing might resolve many of the challenges associated with conventional mechanical wafer testing. These techniques address the increasing demands for internal access of the logic state of a node within a chip under test. Industry has used electronbeam testing in a variety of ways for many years. During the past two decades, many researchers have also investigated techniques based on optical signals, such as photoemissive, electrooptic, and charge density probing, and photoexcitation techniques. This article reviews and explains existing optical contactless technologies and introduces a new test methodology—a fully optical contactless testing technique. The proposed method’s uniqueness lies in the fact that it is a fully optical technique that uses visible light and is completely compatible with standard silicon IC processing. The technique produces results that demonstrate its feasibility and show its advantages over other optical contactless testing methods.